Design a Time Interleaved ADC for 5G V2X Automotive Applications

SFAL

Design a Time Interleaved ADC for 5G V2X Automotive Applications

by SFAL
89 89 people viewed this event.

As semiconductor design quality and reliability is becoming more critical, one way to achieve lower DPPM (defective parts per million) is by increasing manufacturing test coverage.

While Automatic Test Pattern Generation (ATPG) tools achieve high test coverage for scan, compression or built-in self-test (BIST) based designs, there are ATPG untestable faults due to test-mode constraints and design styles such as mixed-signal interfaces, high speed I/O, latches, security and power saving logic.

Synopsys Z01X fault simulation and Verdi fault analysis solutions complements ATPG by providing design for test (DFT) and design engineers a methodology to debug, analyze, measure and increase manufacturing test coverage by fault simulating functional test vectors. This webinar will demonstrate how Z01X and Verdi help achieve and measure additional coverage for ATPG untestable faults in the above-mentioned scenarios starting with results from Synopsys TestMAX ATPG.

Henrik Eriksson is an Application Engineer for fault simulation software tools at Synopsys. He has 10+ years of experience with Z01X fault simulation tools and has worked with chip design, system verification, simulation and emulation for 15+ years before that. He holds a BScEE degree from Malardalen University.

Vin Liao is an Application Engineer for Verdi and PowerReplay at Synopsys. He has 10+ years of experience with Verdi and 5+ years with PowerReplay. He holds a Master’s EE degree from National Tsing Hua University (NTHU).

To register for this event please visit the following URL: https://readytalk.webcasts.com/starthere.jsp?ei=1332962&tp_key=60457ba521&sti=sales →

 

Date And Time

30-08-21 @ 09:30 PM to
31-08-21 @ 11:00 PM
 

Location

Online Event
 

Event Types

 

Event Category

Share With Friends